Learning Objectives:

• Comprehend the components of a timing diagram, including signals, waveforms, time scales, and event markers.
• Understand the role of clock signals in timing diagrams and their importance in synchronizing digital systems.
• Explore the propagation delay of digital components and how it affects signal timing in a timing diagram.

• Instruction: A command given to the microprocessor to perform an operation
• Program : A set of instructions given in a sequential manner to perform a particular task The CPU fetches one instruction from memory at a time & executes it.
• Instruction cycle = Fetch cycle + Execute cycle
• Fetch Cycle : The steps taken by CPU to fetch the opcode from the memory The time taken for fetch cycle is fixed. Execute Cycle : The steps taken by CPU to fetch data & to perform the operation specified in the instruction The time taken for execute cycle is variable which depends on the type of instruction ,i.e. 3 –byte , 2- byte & 1-byte instruction.
• Machine cycle: The time required by the micro processor to complete the operation of accessing memory or I/O device . Operations like : • Opcode fetch • Memory read • Memory write • I/O read • I/O write
• T - states Microprocessor performs an operation in specific clock cycles. Each clock cycle is called as T –States. The number of T – states required to perform an operation is called Machine Cycle .
• MPU Communication and Bus Timing Figure 3: Moving data form memory to MPU using instruction MOV C, A (code machine 4FH = 0100 1111)
• The Fetch Execute Sequence : 1. The μp placed a 16 bit memory address from PC (program counter) to address bus. Figure 4: at T1 – The high order address, 20H, is placed at A15 – A8. – the low order address, 05H, is placed at AD7 - AD0 and ALE is active high. – Synchronously the IO/M is in active low condition to show it is a memory operation. 2. At T2 the active low control signal, RD, is activated so as to activate read operation; it is to indicate that the MPU is in fetch mode operation. MPU Communication and Bus Timing 3. T3: The active low RD signal enabled the byte instruction, 4FH, to be placed on AD7 – AD0 and transferred to the MPU. While RD high, the data bus will be in high impedance mode. 4. T4: The machine code, 4FH, will then be decoded in instruction decoder. The content of accumulator (A) will then copied into C register at time state, T4. MPU Communication and Bus Timing

Solved Example: 9917-01

Which type of timing violation will occur, If a digital IC is operated at clock frequency which is higher than its specified maximum clock frequency?

A. Hold violation

B. Setup violation

C. Propagation delay

D. All of above

Correct Answer: B

Solved Example: 9917-02

In an 8085 system, a PUSH operation requires more clock cycles than a POP operation. Which one of the following options is the correct reason for this?

A. For POP, the data transceivers remain in the same direction as for instruction fetch (memory to processor), whereas for PUSH their direction has to be reversed.

B. Memory write operations are slower than memory read operations in an 8085 based system.

C. The stack pointer needs to be pre-decremented before writing registers in a PUSH, whereas a POP operation uses the address already in the stack pointer.

D. Order of registers has to be interchanged for a PUSH operation, whereas POP uses their natural order.

Correct Answer: C

Solved Example: 9917-03

Which one of the following is not a general operation of machine cycle in a central processing unit ?

A. Fetch

B. Decode

C. Return

D. Store

Correct Answer: C

Solved Example: 9917-04

Which of the following statements with reference to a generic microprocessor is correct?

A. Instruction cycle time period is exactly to machine cycle time period

B. Instruction cycle time period is shorter than machine cycle time period

C. Machine cycle time period is shorter than instruction cycle time period

D. Instruction cycle time period is exactly half of machine cycle time period

Correct Answer: C

Solved Example: 9917-05

Which of the following parameter is improved by introducing pipelining in digital design?

A. Area (Gate count)

B. Maximum clock frequency

C. Power dissipation

D. Noise

Correct Answer: B

Solved Example: 9917-06

When using a sequential code to design a combinational logic in VHDL, if a complete truth table is not defined, the synthesis tool will implement a _______ which is not required.

A. Clock buffer

B. Buffer

C. Flip Flop

D. Latch

Correct Answer: A

In asynchronous mode, the clock is given only to the first flip-flop and each flip-flop produces output one at a atime. The nput for the successive flip-flops depend on the previous ones. These counters are also called ripple counters.

These counters are again categorized as UP and DOWN counters.

Most clocked flip-flops have one or more asynchronous inputs that do not depend on the clock.

Labels Preset and Clear are used for asynchronous inputs.

These asynchronous inputs can be used to set the flipflop to the state 1 or clear to 0 state at anytime, regardless to the conditions at the other inputs.

The asynchrounous inputs are override inputs

• MOD = Modulus, the number of output states of the counter
• MOD = 2$^n$, where n = no. of flip flops required

Solved Example: 9916-01

Consider the following processor design characteristics.
I. Register-to-register arithmetic operations only
II. Fixed-length instruction format
III. Hardwired control unit

Which of the characteristics above are used in the design of a RISC processor?

A. I and II only

B. II and III only

C. I and III only

D. I, II and III

Correct Answer: D

Solved Example: 9916-02

Consider the following statements:
Arithmetic Logic Unit (ALU)
1. Performs arithmetic operations
2. Performs comparisons.
3. Communicates with I/O devices
4. Keeps watch on the system
Which of these statements are correct?

A. 1 Only

B. 1 and 2 only

C. 2 and 3

D. 1 and 4

Correct Answer: B

Solved Example: 9916-03

Advantage of synchronous sequential circuits over asynchronous one is:

A. Lower hardware requirement

B. Better noise immunity

C. Faster operation

D. None of the above

Correct Answer: D

Learning Objectives:

• Learn how static and dynamic hazards occur in digital circuits due to timing or logical imbalances, and how to identify and mitigate them.
• Learn how to identify hazards and race conditions using timing diagrams and waveform analysis.

When a device or system tries to do two or more operations simultaneously when, due to the nature of the device or system, the actions must be performed in the correct order to be performed successfully, a race condition results.

Solved Example: 9915-01

Race around condition is associated with:

A. Combinational circuits

B. Sequential circuits with level triggered clock

C. Sequential circuits

D. Both Sequential and Combinational circuits

Correct Answer: B

Solved Example: 9915-02

What is the condition necessary to avoid Race Around condition in J-K flip flop if clock pulse is $t_p$, propagation delay is $\Delta$t, and clock period is T?

A. Δt > tp > T

B. tp > Δt > T

C. tp < Δt < T

D. Δt < tp < T

Correct Answer: C

Solved Example: 9915-03

The dynamic hazard problem occurs in:

A. Combinational circuit alone

B. Sequential circuit only

C. Both (a) and (b)

D. None of the above

Correct Answer: C